T-PRO International - Whitepaper - What Is Flash?
NVM : Non Volatile Memory
ROM : Read Only Memory
OTP : One Time Programmable ROM
EPROM : Erasable Programmable ROM
EEPROM : Electrically Erasable & Programmable ROM
NVM Hierarchy
Flash Memory
Flash Memory Technologies


A
B
C(and)
C(nand)
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
 
A
B
C(or)
C(nor)
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
Flash Cell Architecture
NAND Cell Technology Scalability
Flash Memory Operation
Performance Comparison
* NAND Flash : High Wright Performance
Pin Configuration
Compatible with Toshiba NAND Flash Memory
Reduced Pin counts by Multiplexed Address and data and command
   (Control pin : 8pin, Data pin : 8pin, Power pin : 4pin)
Identical Pin-out from 4M to 64M(128M to 1G : 48TSOP I)
Array Organization & Address Map
Invalid Block in NAND Flash
Nand Flash may include invalid blocks. Never Write these blocks

(Invalid Block : Block that contain one or more bad bits)

Initial Invalid Block : Original Bad block tested prior to shipping.
> The invalid block mark is written on the 6th byte of each 1st page spare area of the block with 00h data.
> Additional Invalid Blocks may occur during the life time (10 years)
Failure Mode
Detection and Countermeasure sequence
Write
Erase Failure
Pass/Fail-Status Check ------> Block Replacement
Program Failure
Read
Single Bit Failure
Verify ECC ------> ECC Correction
Spec. : min. 98% of the array is guaranteed for valid block over lifetime
Performance : More than 99.8% is verified as valid
Code vs Data Flash in Cell Phone